Position Summary

Stefanini Group is hiring an FPGA Design Engineer with Radio experience for an onsite role in Ottawa, Ontario, Canada.

Contact: Prakhar Goel, ,

Benefits

• 10 days PTO (80 hours, accrual based)
• 9 holidays on average throughout the year
• 3 personal days

Ideal Candidate

FPGA designer engineer with Radio experience working with 4G/5G radios, 7+ years, heavy SystemVerilog/RTL experience, no VHDL.

Tools and Experience

• Altera Quartus
• MATLAB/Simulink for modeling AXI and Ethernet protocols
• Advanced high‑speed experience is desirable

Responsibilities

• Work on complex problems and provide innovative solutions using independent judgment.
• Stay informed on industry trends and communicate vision for long‑term strategy.
• Conduct research, contribute to evaluations, project plans and budgets.
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