Step into Ciena's leading role in high-speed connectivity as a Mixed Signal Design Engineer. Contribute to innovative fiber-optic technology while working in a flexible, people-first environment.
Ciena is looking for an experienced engineer to design cutting-edge Sigma-Delta DAC and ADC systems. This position requires skills in designing SystemVerilog models for high-speed SerDes IP running at 56Gbd to 448Gbd. Collaborate with various teams including hardware, firmware, and signal integrity to support our groundbreaking optical fiber solutions.
Key Responsibilities:
• Design high precision Sigma-Delta DAC and ADC systems
• Create SystemVerilog models for analog macros
• Develop IBIS-AMS models for high-speed SerDes IP
• Draft detailed Design Specification Documents
• Provide support across multiple engineering teams
Requirements:
• BEng/BSc, MEng/MSc, or PhD in relevant fields
• Design experience with CMOS and BiCMOS technologies
• Proficiency with Cade...