This position is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs (System on Chip) designed by Qualcomm. The engineer will be responsible for characterization and developing cost‑effective manufacturing test solutions for HSIO (SERDES) for leading‑edge SoC products in the most advanced processes. These include but are not limited to HSIO PHY testing with automated test equipment (ATE). Main responsibilities include defining and executing the development of test methodologies and characterization of high‑speed SERDES interfaces such as PCIe, USB3, UFS, DP, and MIPI (DSI, CSI). The engineer will develop characterization and test plans, identify DFT and test hardware requirements, and develop ATE tests/routines/programs to execute test plans. The engineer will drive first silicon debug to qualify designs fabricated at external foundries, perform technical data analysis of parametric performance over various operating ...