Lead RTL Design Engineer (ASIC)

Location: Chennai, Tamil Nadu

Experience: 6 to 9 Years

Job Description

6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.

• Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.
• Experience with RTL coding using Verilog/VHDL/System Verilog.
• Experience in micro-architecture & designing cores and ASICs.
• Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc.
• Exposure in scripting (Pearl/Python/TCL).
• Strong debugging capabilities at Synthesis, timing analysis & implementation
• Collaborate closely with cross-function team to research, design and implement performance, constraints and power manage...