Overview

Elevate your career at a leading tech firm as a Senior ASIC Physical Design Engineer. Utilize your 8+ years of expertise in backend implementation and physical design flow.

This role demands end-to-end experience from netlist to GDSII, focusing on Place & Route, timing closure, and tool optimization. You will collaborate with cross-functional teams, leveraging robust hands-on skills in advanced node designs such as 7nm and 5nm. Expect to utilize tools from Synopsys or Cadence, implementing timing analysis and DRC/LVS verification effectively.

Key Responsibilities

• Optimize Place & Route for physical design flow
• Ensure timing closure with setup/hold and ECO implementation
• Perform Static Timing Analysis and report generation
• Conduct power integrity analysis and optimization
• Collaborate with RTL and DFT teams for design efficiency

Requirements

• 8+ years in ASIC Physical Design...