Overview

Sr Principal Design Engineer – Cadence Silicon Solutions Group (SSG). Based in Edinburgh, United Kingdom, reporting to the Design Engineering Group Director. The Cadence IP & Chiplet solutions enable customers to tackle silicon product development in a system context, focusing on product differentiation and reduced time to volume. Cadence pursues industry leading IP & Chiplet solutions to support fast-moving application spaces such as Physical AI, DataCentre and High Performance Computing.

Job Responsibilities

• Provide technical leadership of complex silicon programs consisting of leading-edge IP.
• Collaborate with the Chiplet Architecture team to define next-generation Chiplets.
• Integrate Cadence IP Solutions (e.g., UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision) and partner IP Solutions (e.g., CPUs, ISP, Silicon Monitors, NoCs).
• Lead RTL, Testbench, Formal Analysis and Trial Synthesis activities.
• Ensure Quality ...